LUPXA255A0C200 Datasheet, PDF (16/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Package Information
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
TEXTAL
IA
32 kHz crystal output. No external caps are required. Note [2]
L_DD[12]/
GPIO[70]
LCD display data. (output) Transfers pixel information
ICOCZ ^{from the LCD controller to the external LCD panel.}
RTC clock. (output) Real time clock 1 Hz tick.
Pulled High -
Note[1]
L_DD[13]/
GPIO[71]
ICOCZ
LCD display data. (output) Transfers the pixel
information from the LCD controller to the external LCD
panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
Pulled High -
Note[1]
L_DD[14]/
GPIO[72]
LCD display data. (output) Transfers pixel information
ICOCZ ^{from the LCD controller to the external LCD panel.}
Pulled High -
Note[1]
32 kHz clock. (output) Output from the 32 kHz oscillator.
48MHz/GP[7]
ICOCZ
48 MHz clock. (output) Peripheral clock output derived
from the PLL.
NOTE: This clock is only generated when the USB unit
clock enable is set.
Pulled High -
Note[1]
RTCCLK/
GP[10]
ICOCZ ^{Real time clock. (output) 1 Hz output derived from the}
32 kHz or 3.6864 MHz output.
Pulled High -
Note[1]
3.6MHz/GP[11] ICOCZ ^{3.6864 MHz clock. (output) Output from 3.6864 MHz}
oscillator.
Pulled High -
Note[1]
Pulled High -
32kHz/GP[12] ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator. _Note[1]
Miscellaneous Pins
BOOT_SEL
IC
[2:0]
Boot select pins. (input) Indicates type of boot device. Input
PWR_EN
Power Enable for the power supply. (output) When
OC
negated, it signals the power supply to remove power to Driven High
the core because the system is entering sleep mode.
nBATT_FAULT IC
nVDD_FAULT IC
nRESET
IC
Main Battery Fault. (input) Signals that main battery is
low or removed. Assertion causes PXA255 processor
processor to enter sleep mode or force an imprecise data
exception, which cannot be masked. PXA255 processor
will not recognize a wake-up event while this signal is
asserted. Minimum assertion time for nBATT_FAULT is 1
ms.
Input
VDD Fault. (input) Signals that the main power source is
going out of regulation. nVDD_FAULT causes the
PXA255 processor to enter sleep mode or force an
imprecise data exception, which cannot be masked.
nVDD_FAULT is ignored after a wake-up event until the
power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
Input
Hard reset. (input) Level -sensitive input used to start the
processor from a known address. Assertion terminates
the current instruction abnormally and causes a reset.
When nRESET is driven high, the processor starts
execution from address 0. nRESET must remain low until
the power supply is stable and the internal 3.6864 MHz
oscillator has stabilized.
Input
Note [2]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Input
Driven low while
entering sleep
mode. Driven high
when sleep exit
sequence begins.
Input
Input
Input. Driving low
during sleep will
cause normal
reset sequence
and exit from sleep
mode.
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Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification