LUPXA255A0C200 Datasheet, PDF (32/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Electrical Specifications
4.7.2
Hardware Reset Timing
The timing sequences shown in hardware reset timing for hardware reset assumes stable power
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings
indicated in Section 4.7.1, “Power-On Timing” on page 30.
Figure 4. Hardware Reset Timing
nRESET
t
DHW_NRESET
nRESET_OUT
t
DHW_OUT_A
t
DHW_OUT
NNoottee::nnBBAATTTT__FFAAUULLTTaannddnnVVDDDD__FFAAUULLTTmmuussttbbeehhigighhbbeeffoorre nRESSEETT iiss deasserted
d^oe^r-a^ths^ese^Crt^oe^td^ulo^lar ^wthⁱe^ll P^enX^tA^er2^S5^l5^eep^pro^Mce^os^ds^eor enters sleep mode.
Table 16. Hardware Reset Timing Specifications
Symbol
Description
tDHW_NRESET Minimum assertion time of nRESET
tDHW_OUT_A
Delay between nRESET asserted and
nRESET_OUT asserted
tDHW_OUT
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
Delay between nReset_Out de-asserted
tDHW_NCS0 _{and nCS0 asserted}
Min
0.001
0
Typical Max
0.001
18.1
18.2
400
—
420
Units
ms
ms
ms
ns
4.7.3
Watchdog Reset Timing
Watchdog reset is an internally generated reset and therefore has no external pin dependencies. The
nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for t_{DHW_OUT}.
Refer to Figure 4, “Hardware Reset Timing” on page 32.
4.7.4
GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies
based on the frequency of clock selected, and if the clocks and power manager is in the frequency
change sequence when GPIO reset is asserted (see Section 4.6.1, “32.768-kHz Oscillator
Specifications” on page 28.) Figure 5, “GPIO Reset Timing” on page 33 shows the possible timing
of GPIO reset.
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Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification