82541ER Datasheet, PDF (33/48 Pages) Intel Corporation – 82541ER Gigabit Ethernet Controller

4.5.2
Link Interface Timing
Table 21. Rise and Fall Times
Symbol
Parameter
TR
Clock rise time
TF
Clock fall time
TR
Data rise time
TF
Data fall time
82541ER Gigabit Ethernet Controller
Condition
0.8 V to 2.0 V
2.0 V to 0.8 V
0.8 to 2.0 V
2.0 V to 0.8 V
Min
Max
Unit
0.7
ns
0.7
ns
0.7
ns
0.7
ns
2.0 V
0.8 V
TR
TF
Figure 10. Link Interface Rise/Fall Timing
4.5.3
EEPROM Interface
Table 22. Link Interface Clock Requirements
Symbol
Parameter^a
Min
Typ
Max
Unit
Microwire EESK pulse width
T_PERIOD x
64
ns
TPW
SPI EESK pulse width
T_PERIOD x
32
ns
a. The EEPROM clock is derived from a 125 MHz internal clock.
Table 23. Link Interface Clock Requirements
Symbol
Parameter^a
Min
Typ
Max
Unit
TDOS
EEDO setup time
TCYC*2
ns
TDOH
EEDO hold time
0
ns
a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK.
Datasheet
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