82541ER Datasheet, PDF (29/48 Pages) Intel Corporation – 82541ER Gigabit Ethernet Controller

82541ER Gigabit Ethernet Controller
CL
Figure 2. AC Test Loads for General Output Pins
4.5
Timing Specifications
4.5.1
4.5.1.1
PCI Bus Interface
PCI Bus Interface Clock
Table 18. PCI Bus Interface Clock Parameters
Symbol
Parameter^a
PCI 66 MHz
Min
Max
PCI 33 MHz
Min
Max
Units
TCYC
TH
TL
CLK cycle time
CLK high time
CLK low time
CLK slew rate
RST# slew rate^b
15
30
30
6
11
6
11
1.5
4
1
50
50
ns
ns
ns
4
V/ns
mV/ns
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the
minimum peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system
noise cannot render a monotonic signal to appear bouncing in the switching range.
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Th
0.6 Vcc
Tcyc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
Figure 3. PCI Clock Timing
PCI Clock Timing.vsd
Datasheet
23