82541ER Datasheet, PDF (30/48 Pages) Intel Corporation – 82541ER Gigabit Ethernet Controller

82541ER Gigabit Ethernet Controller
4.5.1.2
PCI/PCI-X Bus Interface Timing
Table 19. PCI Bus Interface Timing Parameters
Symbol
Parameter
PCI 66MHz
Min
Max
TVAL
CLK to signal valid delay: bussed
signals
2
6
TVAL(ptp)
CLK to signal valid delay: point-
to-point signals
2
6
TON
Float to active delay
2
TOFF
Active to float delay
14
TSU
Input setup time to CLK: bussed
signals
3
TSU(ptp)
Input setup time to CLK: point-to-
point signals
5
TH
Input hold time from CLK
0
PCI 33 MHz
Min
Max
2
11
2
12
2
28
7
10, 12
0
Units
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
VTH
PCI_CLK
VTEST
VTL
Output
Delay
VTEST
VSTEP (3.3V Signalling)
output current ≤ leakage current
Tri-State
Output
TON
TOFF
Figure 4. PCI Bus Interface Output Timing Measurement
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Datasheet