82541ER Datasheet, PDF (18/48 Pages) Intel Corporation – 82541ER Gigabit Ethernet Controller

82541ER Gigabit Ethernet Controller
3.5.2
Analog Signals (10)
Symbol Type
Name and Function
MDI[0]+/-
A
MDI[1]+/-
A
MDI[2]+/-
A
MDI[3]+/-
A
IEEE_TEST- A
IEEE_TEST+ A
Media Dependent Interface [0].
1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDI[0]+/- corresponds to BI_DB+/-.
100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in
MDI-X configuration, MDI[0]+/- is used for the receive pair.
10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X
configuration, MDI[0]+/- is used for the receive pair.
Media Dependent Interface [1].
1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDI[1]+/- corresponds to BI_DA+/-.
100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in
MDI-X configuration, MDI[1]+/- is used for the transit pair.
10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X
configuration, MDI[1]+/- is used for the transit pair.
Media Dependent Interface [2].
1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-
X configuration, MDI[2]+/- corresponds to BI_DD+/-.
100BASE_TX: Unused.
10BASE-T: Unused.
Media Dependent Interface [3].
1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-
X configuration, MDI[3]+/- corresponds to BI_DD+/-.
100BASE_TX: Unused.
10BASE-T: Unused.
IEEE test pin output minus. Used to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformance testing.
Analog test pin output plus. Used to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformance testing.
3.6
Test Interface Signals (6)
Symbol
TEST
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
Type
Name and Function
Test Enable. Enables test mode.
I
Normal mode: connect to VSS.
I
JTAG Test Access Port Clock.
I
JTAG Test Access Port Data In.
O
JTAG Test Access Port Data Out.
I
JTAG Test Access Port Mode Select.
JTAG Test Access Port Reset. This is an active low reset signal for JTAG.
I
To disable the JTAG interface, this signal should be terminated using a
100 Ω pull-down resistor to ground. It must not be left unconnected.
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Datasheet