317610-001 Datasheet, PDF (236/342 Pages) Intel Corporation – Express Chipset

Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.36
DCTL—Device Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
A8–A9h
0000h
RW, RO
16 bits
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Bit
15:8
7:5
4
3
2
1
0
Access
RO
RW
RO
RW
RW
RW
RW
Default
Value
Description
0h
000b
0b
0b
0b
0b
0b
Reserved
Max Payload Size (MPS):
000 = 128B max supported payload for Transaction Layer Packets (TLP). As a
receiver, the Device must handle TLPs as large as the set value; as
transmitter, the Device must not generate TLPs exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to support compliance
testing.
Reserved
Unsupported Request Reporting Enable (URRE): When set, this bit allows
signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the Root Control register
when detecting an unmasked Unsupported Request (UR). An ERR_CORR is
signaled when an unmasked Advisory Non-Fatal UR is received. An ERR_FATAL
or ERR_NONFATAL is sent to the Root Control register when an uncorrectable
non-Advisory UR is received with the severity bit set in the Uncorrectable Error
Severity register.
Fatal Error Reporting Enable (FERE): When set, this bit enables signaling of
ERR_FATAL to the Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full scope of
related error reporting.
Non-Fatal Error Reporting Enable (NERE): When set, this bit enables
signaling of ERR_NONFATAL to the Rool Control register due to internally
detected errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
Correctable Error Reporting Enable (CERE): When set, this bit enables
signaling of ERR_CORR to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also control the full
scope of related error reporting.
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Datasheet