317610-001 Datasheet, PDF (202/342 Pages) Intel Corporation – Express Chipset

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2
KT IO/ Memory Mapped Device Specific Registers
[D3:F3]
Table 14.
7.2.1
Note:
KT IO/Memory Mapped Register Address Map
Address Register
Offset Symbol
Register Name
0h
KTRxBR KT Receive Buffer
0h
KTTHR KT Transmit Holding
0h
KTDLLR KT Divisor Latch LSB
1h
KTIER KT Interrupt Enable
1h
KTDLMR KT Divisor Latch MSB
2h
KTIIR KT Interrupt Identification
2h
KTFCR KT FIFO Control
3h
KTLCR KT Line Control
4h
KTMCR KT Modem Control
5h
KTLSR KT Line Status
6h
KTMSR KT Modem Status
7h
KTSCR KT Scratch
Default
Value
Access
00h
RO/V
00h
WO
00h
RW/V
00h RW/V, RO/V
00h
RW/V
01h
RO
00h
WO
03h
RW
00h
RO, RW
00h
RO, RO/CR
00h
RO, RO/CR
00h
RW
KTRxBR—KT Receive Buffer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
0h
00h
RO/V
8 bits
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from ME memory (RBR
FIFO).
Reset: Host System Reset or D3->D0 transition.
Bit
Access
Default
Value
Description
7:0
RO/V
00h
Receiver Buffer Register (RBR): Implements the Data register of the Serial
Interface. If the Host does a read, it reads from the Receive Data Buffer.
202
Datasheet