317610-001 Datasheet, PDF (209/342 Pages) Intel Corporation – Express Chipset

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.10
Note:
KTLSR—KT Line Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
5h
00h
RO, RO/CR
8 bits
This register provides status information of the data transfer to the Host. Error
indication, etc., are provided by the hardware(HW)/firmware(FW) to the host via this
register.
Reset: Host system reset or D3->D0 transition.
Bit
Access
Default
Value
Description
7
RO
6
RO
5
RO
4
RO/CR
3:2
RO
1
RO/CR
0
RO
0b
0b
0b
0b
00b
0b
0b
RX FIFO Error (RXFER): This bit is cleared in non FIFO mode. Bit is connected
to the BI bit in FIFO mode.
Transmit Shift Register Empty (TEMT): This bit is connected by hardware to
bit 5 (THRE) of this register
Transmit Holding Register Empty (THRE): The bit is always set when the
mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the
THR operation is enabled by the FW.
This bit has acts differently in the different modes:
• Non FIFO Mode: This bit is cleared by hardware when the Host writes to the THR
registers and set by hardware when the FW reads the THR register.
• FIFO Mode: This bit is set by hardware when the THR FIFO is empty, and cleared by
hardware when the THR FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
Break Interrupt (BI): This bit is cleared by hardware when the LSR register is
being read by the Host.
This bit is set by hardware in two cases:
• FIFO Mode: The FW sets the BI bit by setting the SBI bit in the KTRIVR register (See
KT AUX registers)
• Non FIFO Mode: the FW sets the BI bit by setting the BIA bit in the KTRxBR register
(see KT AUX registers)
Reserved
Overrun Error (OE): This bit is cleared by hardware when the LSR register is
being read by the Host. The FW typically sets this bit, but it is cleared by
hardware when the host reads the LSR.
Data Ready (DR):
• Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared by
hardware when the RBR register is being Read by the Host.
• FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared by
hardware when the RBR FIFO is empty.
This bit is reset on Host System Reset or D3->D0 transition
Datasheet
209