317610-001 Datasheet, PDF (164/342 Pages) Intel Corporation – Express Chipset

Host-Primary PCI Express* Bridge Registers (D1:F0)
6.25
PM_CAPID1—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
80–83h
C8039001h
RO
32 bits
Bit
31:27
26
25
24:22
21
20
19
18:16
15:8
7:0
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
Description
19h
0b
0b
000b
0b
0b
0b
011b
90h
01h
PME Support (PMES): This field indicates the power states in which this device
may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This
device is not required to do anything to support D3hot & D3cold, it simply must
report that those states are supported. Refer to the PCI Power Management 1.1
specification for encoding explanation and other power management details.
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that the D2
power management state is NOT supported.
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that the D1
power management state is NOT supported.
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are no
3.3Vaux auxiliary current requirements.
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special
initialization of this device is NOT required before generic class device driver is to
use it.
Auxiliary Power Source (APS): Hardwired to 0.
PME Clock (PMECLK): Hardwired to 0 to indicate this device does NOT support
PMEB generation.
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management Interface Specification.
Pointer to Next Capability (PNC): This contains a pointer to the next item in
the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI) capability at 90h.
Capability ID (CID): Value of 01h identifies this linked list item (capability
structure) as being for PCI Power Management registers.
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Datasheet