GD82559C Datasheet, PDF (15/60 Pages) Intel Corporation – Intel-Based Electronic Classroom Student Computing Station Based on the Intel® Celeron™ Processor and Intel® 810 Chipset

Intel-Based Electronic Classroom Student Computing Station
5.2.1
5.2.1.1
The Intel^® 82810 Graphics Memory Controller Hub (GMCH0)
The Intel 810 chipset provides a rich and robust 2-D and 3-D graphics using an integrated chipset
design that utilizes second-generation graphics technology. At the core of the 810 chipset is a
memory controller with built-in graphics technology. The Intel 810 chip optimizes system memory
arbitration, similar to AGP technology, resulting in a more responsive and cost-effective system.
The 82810 Graphics Memory Controller Hub (GMCH0) features Intel graphics technology and
software drivers and uses Direct AGP (integrated AGP) to create vivid 2-D and 3-D effects and
images. The 82810 chip features integrated Hardware Motion Compensation to improve soft DVD
video quality and a digital video out port that enables connection to traditional TVs or the new
space-saving digital flat panel displays.
Intel Dynamic Video Memory Technology (DVMT) is an architecture that offers breakthrough
performance for the Value PC segment through efficient memory utilization and Direct AGP. The
system OS uses the Intel software drivers and intelligent memory arbiter to support richer graphics
applications.
The System Manageability Bus allows networking equipment to monitor the 810-chipset platform.
Using ACPI specifications, the system manageability function enables low-power sleep mode and
conserves energy when the system is idle.
Design Notes for the Intel^® 82810 GMCH0
The GMCH ball assignment and ICH ball assignment have been optimized to simplify hub
interface routing. It is recommended that the hub interface signals are routed directly from the
GMCH0 to the ICH on the top signal layer. The hub interface has two signal groups:
• Data Signals: HL[10:0]
• Strobe Signals: HL_STB, HL_STB# (differential strobe pair)
There are no pull-ups or pull-downs required on the hub interface.
Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of
20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for
navigation around components or mounting holes. To break out of the GMCH0 and the ICH, the
hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils.
The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils within 0.3”
of the GMCH0/ICH components. The maximum trace length for the hub interface data signals is
7”. These signals should each be matched within ±0.1” of the HL_STB and HL_STB# signals.
Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed
20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The
maximum length for the strobe signals is 7” and the two strobes should be the same length.
Additionally, the trace length for each data signal should be matched to the trace length of the
strobes with ±0.1”.
HREF is the hub interface reference voltage. It is 0.5 * 1.8 V = 0.9 V ±2%. It can be generated
locally, or a single HREF divider can be used. Each divider consists of a DC element and an AC
element. The resistors in the DC element should be equal in value and rated at 1% tolerance. The
value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained
over the entire input leakage specification. The resistors in the AC element of the resistor divider
should be no greater than 80 Ω and the capacitors should be 500 pF. Additionally, the reference
voltage should be bypassed to ground at each component with a 0.1 uF capacitor.
Application Note
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