GD82559C Datasheet, PDF (13/60 Pages) Intel Corporation – Intel-Based Electronic Classroom Student Computing Station Based on the Intel® Celeron™ Processor and Intel® 810 Chipset

Intel-Based Electronic Classroom Student Computing Station
5.0
Design Consideration of Intel-Based Electronic
Classroom Student Computing Station Hardware
5.1
5.1.1
Figure 3.
Intel^® Celeron™ Processor
This reference configuration supports the Intel Celeron processor at 300, 366 MHz and 433 MHz
in a Plastic Pin Grid Array (PPGA) package.
The Intel Celeron processor PPGA package implements a Dynamic Execution micro-architecture
and executes MMX™ media technology instructions for enhanced media and communication
performance. The Intel Celeron processor PPGA is based on the P6 family processor core and is
provided in a PPGA package for use in low cost systems in the value PC and Intel-based electronic
classroom student computing station market segments. The Intel Celeron processor PPGA utilizes
the AGTL+ system bus used by the Pentium^® II processor with support limited to single-processor
systems. The Intel Celeron processor PPGA includes an integrated 128 Kbyte second level cache
with separate 16 Kbyte instruction and 16 Kbyte data level-one caches. The second level cache is
capable of caching 4 Gbytes of system memory.
Design Notes for the Intel^® Celeron™ Processor
The schematics use a Single Ended Termination (SET) network topology in which the termination
resistors are located at only the PPGA (processor) side to reduce the system cost, solution space,
and ringing effect. In the SET topology, the termination should be placed close to the processor
either on the motherboard or on the processor substrate. No termination is present at the chipset end
of the network.
Topology for Single Processor Designs with Single End Termination (SET)
V_TT
L2^††
Intel® 810
L1^†
Chipset
† - 1.9" <L1 <5.0"
†† - 0.5" <L2 <2.0"
A7494-01
Application Note
13