83C51KB Datasheet, PDF (15/19 Pages) Intel Corporation – HIGH PERFORMANCE KEYBOARD MICROCONTROLLER

83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 7. D.C. Characteristics (Continued)
Symbol
Parameter
Min
Typical
(note 1)
Max
Unit
Test
Condition
I_CC
Power Supply Current:
Active Mode at 6MHz
Idle Mode at 6MHz
Power Down Mode
7
12
mA RST, EA# to
V_CC
2
5
mA RST, EA# to
V_SS
10
50
µA RST, EA# to
V_SS
(RCIN pin to
external resis-
tor, all other
pins are no
connect)
V_POR Power on reset crossover
2.4
3
3.6
V
NOTE:
1. Typical values are obtained using V_CC=5.0V, TA=25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, I_OL must be externally limited as follow:
Maximum I_OL per Port Pin—Port 0, 1, 2, P3.1-P3.3:
10mA
Maximum I_OL per Port Pin—P3.4-P3.7:
22mA
Maximum I_OL per 8-bit port—Port 0-2:
15mA
Ports 3:
95mA
Maximum Total I_OL for AllOutput Pins:
110mA
If I_OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis-
charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where
capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the 0.9 V_CC
specification when the address lines are stabilizing.
V_CC – 0.5
0.7 V_CC
0.45 V
0.2 V_CC – 0.1
T_CHCL
T_CLCH
T_CHCX
T_CLCX
T_CLCL
Figure 5. External Clock Drive
A4252-01
15