83C51KB Datasheet, PDF (13/19 Pages) Intel Corporation – HIGH PERFORMANCE KEYBOARD MICROCONTROLLER

83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.1 D.C. Characteristics
Symbol
Parameter
Table 7. D.C. Characteristics
Min
Typical
(note 1)
Max
Unit
Test
Condition
V_IL
Input Low Voltage (except
-0.5
EA#, RCIN, RST)
0.2 V_CC -0.1
V
V_IL1
Input Low Voltage RST
0
V_IL2
Input Low Voltage EA#
-0.5
V_IL3
Input Low Voltage RCIN
V_IH
Input High Voltage (except
0.2V_CC+
EA#, RCIN, RST)
0.9
0.2 V_CC -0.3 V
0.5
V
V_CC/3
V
V_CC+0.5
V
V_IH1
Input High Voltage (EA#,
RST)
0.7V_CC
V_CC+0.5
V
V_IH2
Input High Voltage RCIN
2V_CC/3
I_IH = 8 mA
when external
clock source is
used on RCIN
V_OL
Output Low Voltage (Port 0, 1,
2, 3, ALE, PSEN# except
P3.4/LED0, P3.5/LED1,
P3.6/LED2, P3.7/LED3)
0.3
0.45
1.0
V I_OL=200 µA
I_OL=3.2 mA
I_OL=7.0 mA
(note 2,3)
I_OL
Output Low Current
(P3.4/LED0, P3.5/LED1,
6
13
P3.6/LED2, P3.7/LED3 only)
22
mA V_OL=3.0 V
V_OH
Output High Voltage (Port 0, V_CC-0.3
1, 2, 3, ALE, PSEN#, except
V_CC-0.7
P3.0, P3.2, P3.3)
V_CC-1.5
V I_OH= -25 µA
I_OH= -65 µA
I_OH= -100 µA
(note 4)
NOTE:
1. Typical values are obtained using V_CC=5.0V, TA=25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, I_OL must be externally limited as follow:
Maximum I_OL per Port Pin—Port 0, 1, 2, P3.1-P3.3:
10mA
Maximum I_OL per Port Pin—P3.4-P3.7:
22mA
Maximum I_OL per 8-bit port—Port 0-2:
15mA
Ports 3:
95mA
Maximum Total I_OL for AllOutput Pins:
110mA
If I_OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis-
charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where
capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the 0.9 V_CC
specification when the address lines are stabilizing.
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