83C51KB Datasheet, PDF (14/19 Pages) Intel Corporation – HIGH PERFORMANCE KEYBOARD MICROCONTROLLER

83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 7. D.C. Characteristics (Continued)
Symbol
Parameter
Min
V_OH1
V_OH2
R_RST
R_CD
Output High Voltage (P3.0,
P3.2, P3.3 without 1.8K Ohm
pullup)
Output High Voltage (P3.0,
P3.2, P3.3 with 1.8K Ohm pul-
lup)
Reset Pulldown Resistor
Pull Up Resistance (P3.0,
P3.2, P3.3 with 1.8K Ohm pul-
lup)
V_CC-0.3
V_CC-0.7
V_CC-1.5
V_CC-0.3
V_CC-0.7
V_CC-1.5
40
1.2
Typical
(note 1)
1.8
Max
225
2.9
Unit
Test
Condition
V
V
K Ohm
I_OH= -8 µA
I_OH= -25 µA
I_OH= -50 µA
I_OH= -0.15 mA
I_OH= -0.50 mA
I_OH= -1.0 mA
K Ohm
C_IO
Pin Capacitance
I_IL
Logical 0 Input Current (Port
0, 1, 2, 3, except P3.0, P3.2,
P3.3)
10
pF @1MHz, 25°C
-50
µA V_IN=0.45V
I_IL1
Logical 0 Input Current (P3.0,
P3.2, P3.3 without 1.8K Ohm
pullup)
-250
µA V_IN=0.45V
I_IL2
Logical 0 Input Current (P3.0,
-1.5
P3.2, P3.2 with 1.8K Ohm pul-
lup)
-4.5
mA V_IN=0.45V
I_TL
Logical 1-to-0 Transiton Cur-
rent (Port 0, 1, 2, 3)
-650
µA V_IN=2.0V
I_TL1
Logical 1-to-0 Transition Cur-
rent (P3.0, P3.2 or P3.3 with
1.8K Ohm pullups)
-4.5
mA V_IN = 2.0V
NOTE:
1. Typical values are obtained using V_CC=5.0V, TA=25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, I_OL must be externally limited as follow:
Maximum I_OL per Port Pin—Port 0, 1, 2, P3.1-P3.3:
10mA
Maximum I_OL per Port Pin—P3.4-P3.7:
22mA
Maximum I_OL per 8-bit port—Port 0-2:
15mA
Ports 3:
95mA
Maximum Total I_OL for AllOutput Pins:
110mA
If I_OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis-
charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where
capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the 0.9 V_CC
specification when the address lines are stabilizing.
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