21154 Datasheet, PDF (121/168 Pages) Intel Corporation – 21154 PCI-to-PCI Bridge

21154 PCI-to-PCI Bridge
15.1.6
15.1.7
15.1.8
15.1.9
Programming Interface Register—Offset 09h
This section describes the programming interface register.
Dword address = 08h
Byte enable p_cbe_l<3:0> = xx0xb
Dword Bit
Name
R/W
Description
No programming interfaces have been defined for
15:8
Programming
interface
R
PCI-to-PCI bridges.
Reads as 0.
Subclass Code Register—Offset 0Ah
This section describes the subclass code register.
Dword address = 08h
Byte enable p_cbe_l<3:0> = x0xxb
Dword Bit
Name
R/W
23:16
Subclass code
R
Description
Reads as 04h to indicate that this bridge device
is a PCI-to-PCI bridge.
Base Class Code Register—Offset 0Bh
This section describes the base class code register.
Dword address = 08h
Byte enable p_cbe_l<3:0> = 0xxxb
Dword Bit
31:24
Name
R/W
Base class
code
R
Description
Reads as 06h to indicate that this device is a bridge device.
Cache Line Size Register—Offset 0Ch
This section describes the cache line size register.
Dword address = 0Ch
Byte enable p_cbe_l<3:0> = xxx0b
Dword Bit
7:0
Name
Cache
line size
R/W
R/W
Description
Designates the cache line size for the system in units of 32-bit
Dwords. Used for prefetching memory read transactions and
for terminating memory write and invalidate transactions.
The cache line size should be written as a power of 2. If the
value is not a power of 2 or is greater than 16, the 21154
behaves as if the cache line size were 0.
Reset value: 0.
Datasheet
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