21154 Datasheet, PDF (100/168 Pages) Intel Corporation – 21154 PCI-to-PCI Bridge

21154 PCI-to-PCI Bridge
low priority group. Using this example, if all requests are always asserted, the highest priority
rotates among the masters in the following fashion (high priority members are given in italics, low
priority members, in boldface type):
B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, and so
on.
Figure 18. Secondary Arbiter Example
m2
lpg
m1
B
m0
m3 _m4
Note:
B – 21154
mx – Bus Master Number
lpg – Low Priority Group
m8
m7
m5
m6
Arbiter Control Register = 10 0000 0111b
LJ-05003.AI4
Each bus master, including the 21154, can be configured to be in either the low priority group or
the high priority group by setting the corresponding priority bit in the arbiter control register in
device-specific configuration space. Each master has a corresponding bit. If the bit is set to 1, the
master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low
priority group. If all the masters are assigned to one group, the algorithm defaults to a straight
rotating priority among all the masters. After reset, all external masters are assigned to the low
priority group, and the 21154 is assigned to the high priority group. The 21154 receives highest
priority on the target bus every other transaction, and priority rotates evenly among the other
masters.
Priorities are reevaluated every time s_frame_l is asserted, that is, at the start of each new
transaction on the secondary PCI bus. From this point until the time that the next transaction starts,
the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If
a grant for a particular request is asserted, and a higher priority request subsequently asserts, the
arbiter deasserts the asserted grant signal and asserts the grant corresponding to the new higher
priority request on the next PCI clock cycle. When priorities are reevaluated, the highest priority is
assigned to the next highest priority master relative to the master that initiated the previous
transaction. The master that initiated the last transaction now has the lowest priority in its group.
If the 21154 detects that an initiator has failed to assert s_frame_l after 16 cycles of both grant
assertion and a secondary idle bus condition, the arbiter deasserts the grant. That master does not
receive any more grants until it deasserts its request for at least one PCI clock cycle.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant
signal in the same PCI cycle in which it deasserts another. It deasserts one grant, and then asserts
the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is,
either s_frame_l or s_irdy_l is asserted, the arbiter can deassert one grant and assert another grant
during the same PCI clock cycle.
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Datasheet