21154 Datasheet, PDF (111/168 Pages) Intel Corporation – 21154 PCI-to-PCI Bridge

13.0 PCI Power Management
The 21154¹ incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.0. These features include:
• PCI power management registers using the enhanced capabilities port (ECP) address
mechanism
• Support for D0, D3_hot, and D3_cold power management states
• Support for D0, D1, D2, D3_hot, and D3_cold power management states for devices behind the
bridge
• Support of the B2 secondary bus power state when in the D3_hot power management state
Table 35 shows the states and related actions that the 21154 performs during power management
transitions. (No other transactions are permitted.)
Table 35. Power Management Transitions
Current State
Next State
D0
D3_cold
D0
D3_hot
D0
D2
D0
D1
D3_hot
D3_hot
D3_cold
D0
D3cold
D0
Action
Power has been removed from the 21154. A power-
up reset must be performed to bring the 21154 to D0.
If enabled to do so by the bpcce pin, the 21154 will
disable the secondary clocks and drive them low.
Unimplemented power state. The 21154 will ignore
the write to the power state bits (power state remains
at D0).
Unimplemented power state. The 21154 will ignore
the write to the power state bits (power state remains
at D0).
The 21154 enables secondary clock outputs and
performs an internal chip reset. Signal s_rst_l will not
be asserted. All registers will be returned to the reset
values and buffers will be cleared.
Power has been removed from the 21154. A power-
up reset must be performed to bring the 21154 to D0.
Power-up reset. The 21154 performs the standard
power-up reset functions as described in
Section 11.0.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do
not pass through PCI-to-PCI bridges.
1. The 21154-AA does not include these features.
Datasheet
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