80C186EB Datasheet, PDF (12/59 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
DT R
LOCK
HOLD
HLDA
NCS
(N C )
ERROR
(N C )
PEREQ
(N C )
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
Pin
Type
O
O
I
O
O
I
I
O
O
O
Input
Type
A(L)
A(L)
A(L)
Table 3 Pin Descriptions (Continued)
Output
States
Description
H(Z)
R(Z)
P(X)
Data Transmit Receive output controls the direction of a
bi-directional buffer in a buffered system DT R is only
available for the PLCC package
H(Z)
R(WH)
P(1)
LOCK output indicates that the bus cycle in progress is not
to be interrupted The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix
H(1)
HoLD Acknowledge output to indicate that the processor
R(0)
has relinquished control of the local bus When HLDA is
P(0)
asserted the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly
H(1)
Numerics Coprocessor Select output is generated when
R(1)
accessing a numerics coprocessor NCS is not provided on
P(1)
the QFP or SQFP packages This signal does not exist on
the 80C188EB 80L188EB
ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation ERROR is not provided
on the QFP or SQFP packages This signal does not exist
on the 80C188EB 80L188EB
CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending PEREQ is not provided on the QFP or SQFP
packages This signal does not exist on the 80C188EB
80L188EB
H(1)
Upper Chip Select will go active whenever the address of
R(1)
a memory or I O bus cycle is within the address limitations
P(1)
programmed by the user After reset UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH
H(1)
Lower Chip Select will go active whenever the address of
R(1)
a memory bus cycle is within the address limitations
P(1)
programmed by the user LCS is inactive after a reset
H(X) H(1)
R(1)
P(X) P(1)
These pins provide a multiplexed function If enabled each
pin can provide a Generic Chip Select output which will go
active whenever the address of a memory or I O bus cycle
is within the address limitations programmed by the user
When not programmed as a Chip-Select each pin may be
used as a general purpose output Port As an output port
pin the value of the pin can be read internally
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
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