80C186EB Datasheet, PDF (11/59 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions (Continued)
Pin
Name
Pin Input Output
Type Type States
Description
A18 16
IO
A19 ONCE
(A15 A8)
(A18 16)
(A19 ONCE)
A(L) H(Z) These pins provide multiplexed Address during the address
R(WH) phase of the bus cycle Address bits 16 through 19 are presented
P(X) ^{on these pins and can be latched using ALE These pins are}
driven to a logic 0 during the data phase of the bus cycle On the
80C188EB A15 – A8 provide valid address information for the
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
S2 0
O
H(Z)
R(Z)
P(1)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)
ALE
O
H(0) Address Latch Enable output is used to strobe address
R(0) information into a transparent type latch during the address phase
P(0) ^{of the bus cycle}
BHE
O
(RFSH)
H(Z)
R(Z)
P(X)
Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
A0 have the following logical encoding
A0 BHE Encoding (for the 80C186EB 80L186EB only)
0
0
Word Transfer
0
1
Even Byte Transfer
1
0
Odd Byte Transfer
1
1
Refresh Operation
On the 80C188EB 80L188EB RFSH is asserted low to indicate a
refresh bus cycle
RD
O
H(Z) ReaD output signals that the accessed memory or I O device
R(Z) must drive data information onto the data bus
P(1)
WR
O
H(Z) WRite output signals that data available on the data bus are to be
R(Z) written into the accessed memory or I O device
P(1)
READY
I A(L)
S(L)
READY input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
correctly programming the Chip-Select Unit
DEN
O
H(Z)
R(Z)
P(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
to be transferred on the bus
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
11
11