80960SB Datasheet, PDF (11/38 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS

80960SB
1.1.9 Interrupt Handling
The 80960SB can be interrupted in one of two ways:
by the activation of one of four interrupt pins or by
sending a message on the processor’s data bus.
The 80960SB is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip
interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
1.1.10 Debug Features
The 80960SB has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers, the Process-Controls Word and the Trace-
Controls Word. By setting bits in these control words,
a software debug monitor can closely control how
the processor responds during program execution.
The 80960SB provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automati-
cally called.
The 80960SB also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960SB
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960SB’s
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.11 Fault Detection
The 80960SB has an automatic mechanism to
handle faults. Fault types include floating point, trace
and arithmetic faults. When the processor detects a
fault, it automatically calls the appropriate fault
handling routine and saves the current instruction
pointer and necessary state information to make
efficient recovery possible. Like interrupt handling
routines, fault handling routines are usually written to
meet the needs of specific applications and are often
included as part of the operating system or kernel.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. For example, a floating point fault may have the
subtype set to an Overflow or Zero-Divide fault. The
fault handler can use this specific information to
respond correctly to the fault.
1.1.12 Built-in Testability
Upon reset, the 80960SB automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960SB asserts its FAIL pin
and will not begin program execution. Self test takes
approximately 47,000 cycles to complete.
System manufacturers can use the 80960SB’s self-
test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.13 CHMOS
The 80960SB is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semicon-
ductor) process. The 80960SB is available at 10
MHz in the QFP package and at 10 and 16 MHz in
the PLCC package.
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