273159-006 Datasheet, PDF (1/86 Pages) Intel Corporation – 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

80960JA/JF/JD/JS/JC/JT 3.3 V
Embedded 32-Bit Microprocessor
Product Features
Datasheet
s Code Compatible with all 80960Jx
Processors
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is:
1x the Bus Clock for 80960JA/JF/JS
2x the Bus Clock for 80960JD/JC
3x the Bus Clock for 80960JT
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s Two-Way Set Associative Instruction
Cache
— 80960JA - 2 Kbyte
— 80960JF/JD - 4 Kbyte
— 80960JS/JC/JT - 16 Kbyte
— Programmable Cache-Locking
Mechanism
s Direct Mapped Data Cache
— 80960JA - 1 Kbyte
— 80960JF/JD - 2 Kbyte
— 80960JS/JC/JT - 4 Kbyte
— Write Through Operation
s On-Chip Stack Frame Cache
— Seven Register Sets May Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s 3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
s High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI#
— Up to 240 Vectors in Expanded Mode
s Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— Internal Interrupt Sources
s Halt Mode for Low Power
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack
(PQFP)
— 196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Order Number: 273159-006
August 2004