TLE7273-2_14 Datasheet, PDF (9/26 Pages) Infineon Technologies AG – Low Dropout Voltage Regulator

TLE7273-2
Block Description and Electrical Characteristics
is in the very first turn after power up a long open window with tmax = 4 * t_OW. In the following turns, the timing
corresponds to the standard timing setting as described in the specification.
When a valid trigger signal is detected during the open window a closed window is initialized immediately. A trigger
signal within the closed window is interpreted as a pretrigger failure and results in a reset. After the closed window
the open window with the duration t_OW is started again. The open window lasts at minimum until the trigger process
has occurred, at maximum t_OW is 32 ms (typ. value with fast timing).
A HIGH to LOW transition of the watchdog trigger signal at pin WDI is considered as a valid trigger pulse.
See Figure 7: To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples
(sample period t_sam typ. 0.5 ms) are decoded as a valid trigger .
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. The triggering is correct also, if the first three samples (two HIGH one LOW) of the
trigger pulse at pin WDI are inside the closed window and only the fourth sample (the second LOW sample) is
taken in the open window.
After turning OFF the Watchdog by output current reduction, RO remains high. (see also the signal diagram in
Figure 6). After turning ON the WWD again by exceeding the current threshold, the logic cycle starts again with
the Ignore Window and goes then into the “1st. long open window”. This 1st long OW is maximum 4 * t_OW long and
allows the re-synchronisation between the micro controller and the WWD timing. The 1st. long OW is closed by
the first valid trigger on WDI from the mirco controller. This trigger ensures the synchronisation. As soon as this
trigger is done, the micro controller timing must be stable and correspondent to t_WD.
Reset
Trigger
Always
Ignore
Window
No Trigger During
Open Window
Trigger During
Closed Window
Always
Closed
Window
Trigger
No Trigger
Open
Window
IQ > 5mA
Watchdog
OFF
IQ < 0.5mA
Always
WM1
L
WM2
L
Window Watchdog Mode Fast
Reset Mode
Fast
L
H
Slow
Slow
H
H
L
H
Fast Off
Slow Slow
AEA03527_1.VSD
Figure 5 Window Watchdog State Diagram, Watchdog and Reset Modes
Data Sheet
9
Rev. 1.21, 2014-11-19