TLE7273-2_14 Datasheet, PDF (4/26 Pages) Infineon Technologies AG – Low Dropout Voltage Regulator

TLE7273-2
3
Pin Configuration
3.1
Pin Assignment (PG-DSO-14)
Pin Configuration
Figure 2
RO
GND
GND
GND
GND
WM2
WM1
1
14 EN
2
13 I
3
12 GND
4
11 GND
5
10 GND
6
9Q
7
8 WDI
AEP02113_7273
Pin Assignment PG-DSO-14 (top view)
3.2
Pin Definitions and Functions (PG-DSO-14)
Table 1
Pin No.
1
2-5, 10-12
7
6
8
9
13
14
Pin Definitions and Functions
Symbol
Function
RO
Reset Output
TLE7273-2GV33, TLE7273-2GV26: open drain output;
TLE7273-2GV50: integrated 20 kΩ pull-up resistor to output Q;
leave open if not needed
GND
Ground
connect pin 2 and 3 to GND;
connect pin 4-5 and 10-12 to heat sink area with GND potential
WM1
Watchdog Mode Bit 1
watchdog and reset mode selection, see “Window Watchdog State
Diagram, Watchdog and Reset Modes” on Page 9;
connect to Q or GND
WM2
Watchdog Mode Bit 2
watchdog and reset mode selection, see “Window Watchdog State
Diagram, Watchdog and Reset Modes” on Page 9;
connect to Q or GND
WDI
Watchdog Input
trigger input for watchdog pulses;
to turn off watchdog connect to GND and connect pin WM1 and WM2 to Q
Q
Output Voltage
block to GND with a ceramic capacitor close to the IC terminals, respecting
the values given for its capacitance and ESR in “Functional Range” on
Page 7
I
Input Voltage
block to ground directly at the IC with a 100 nF ceramic capacitor
EN
Enable Input
low level disables the IC;
integrated pull-down resistor to GND
Data Sheet
4
Rev. 1.21, 2014-11-19