HYS64D64020GBDL Datasheet, PDF (8/25 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Modules

HYS64D64020GBDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3 Pin Definitions and Functions
Symbol
Type¹⁾
A0 - A12
I
BA0, BA1
I
DQ0 - DQ63
I/O
RAS, CAS, WE
I
CKE0 - CKE1
I
DQS0 - DQS7
I/O
CK0 - CK1,
I
CK0 - CK1
I
DM0 - DM8
I
S0, S1 ²⁾
I
V_DD
V_SS
V_DDQ
V_DDID
V_REF
V_DDSPD
SCL
PWR
GND
PWR
PWR
AI
PWR
I
SDA
I/O
SA0 - SA2
I
NC
NC
NU
NU
Function
Address Inputs
Bank Address
Data Input/Output
Command Input
Clock Enable
SDRAM Data Strobe
SDRAM Clock (true signal)
SDRAM Clock (complementary signal)
Data Mask
Chip Select
Power (+ 2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
Serial bus data line
slave address select
Not Connected
Not Usable, reserved for future use
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected; NU: Not Usable
2) CKE1 and S1 are used on two bank modules only
Table 4
Density
512 MB
Address Format
Organization Memory
Ranks
64M × 64
2
SDRAMs
32M × 8
# of
# of row/bank/
SDRAMs columns bits
16
13 / 2 /10
Refresh Period Interval
8K
64 ms 7.8 µs
Data Sheet
8
V1.0, 2003-08