V23815-U1306-MXXX Datasheet, PDF (6/9 Pages) Infineon Technologies AG – Parallel Optical Link: PAROLI T X AC, 1.6 Gbit/s

Notes
1. Level Diagram:
mV
1475
925
|VID|
LVDS Output Enable
0.8 V
2.0 V
Data Out
data valid
data Low
data valid
t3
t4
Time
2. |V_OD|=|(output voltage of non-inverted output minus output voltage
of inverted output)|.
3. V_OS=¹/2 (output voltage of inverted output + output voltage of non-
inverted output).
4. LVDS output must be terminated differentially with R_t.
5. Measured between 20% and 80% level with a maximum capacitive
load of 5 pF.
6. With no optical input jitter.
7. At sensitivity limit of -17.0 dBm at infinite ER.
8. Source current
9. Sink current
10.With input channel-to-channel skew 0 ps.
Parameter
Symbol Min. Typ. Max. Units
Data Rate
Per Channel⁽¹⁾
D_R
250
1600 Mbit/s
Sensitivity
(Average Power)⁽²⁾
P_IN
–17.0 dBm
Saturation
(Average Power)⁽²⁾
P_SAT –6.0
Signal Detect
Assert Level⁽³⁾
P_SDA
–18.0
Signal Detect
Deassert Level⁽³⁾
P_SDD –26.0
Signal Detect
Hysteresis⁽³⁾
P_SDA– 1.0 2.5 4.0 dB
P_SDD
Return Loss of Receiver A_RL
12
Notes
Optical parameters valid for each channel.
1. Optical input data should be DC balanced within 100 ns. Maximum
time interval of consecutive ’0’s and ’1’s (run length) should not
exceed 50 ns.
2. Measured with a DC balanced pattern (within 144 bits) with a maxi-
mum run length of 72 bits. BER=10 ^–12. Extinction ratio=infinite.
3. P_SDA: Average optical power when SD switches from unactive to
active.
P_SDD: Average optical power when SD switches from active to
unactive.
Figure 4. Timing diagram
Data Out 1, 12
Signal Detect 1
t1
t2
Signal Detect 12
Parameter
Symbol
Max.
Units
Signal Detect
Deassert Time
t₁
10
µs
Signal Detect
t₂
Assert Time
LVDS Output Enable off t₃
Delay Time
20
ns
LVDS Output Enable on t₄
Delay Time
Receiver Pin Description
Pin# Pin Name Level/Logic Description
1
V_EE
2
V_CC1
Ground
Power supply voltage of
preamplifier
3
V_CC2
Power supply voltage of analog
circuitry
4
t.b.l.o.
to be left open
5
-RESET LVCMOS In High=normal operation
Low=sets all Data Outputs
to low
This input has an internal
pull-up resistor which pulls to
high level when this input is
left open
6
SD1
LVCMOS
Out
Signal Dectect on fiber #1.
High=signal of sufficient AC
power is present on fiber #1
Low=signal on fiber #1 is
insufficient
7
V_CC3
Power supply voltage of
digital circuitry
8
V_EE
9
t.b.l.o.
Ground
to be left open
10
V_EE
Ground
11
V_EE
Ground
12
V_EE
Ground
13 DO01P LVDS Out Data Output #1, non-inverted
14 DO01N LVDS Out Data Output #1, inverted
15
V_EE
Ground
16
V_EE
Ground
17 DO02P LVDS Out Data Output #2, non-inverted
18 DO02N LVDS Out Data Output #2, inverted
19
V_EE
Ground
20
V_EE
Ground
21 DO03P LVDS Out Data Output #3, non-inverted
22 DO03N LVDS Out Data Output #3, inverted
Fiber Optics
V23814/15-U1306-M130 Parallel Optical Link: PAROLI™ Tx/Rx AC, 1.6 Gbit/s
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