ICL5101_16 Datasheet, PDF (6/44 Pages) Infineon Technologies AG – Resonant controller IC with PFC for LED driver

ICL5101
Pin Configuration and Description
1.4
PIN Functionality
Table 1. Pin Definitions and Functions
Symbol
Pin
LSGD
1
LSCS
2
VCC
3
Function
Low-side gate drive
The gate of the low-side MOSFET in a RESONANT inverter topology is
controlled by this pin. There is an active L-level during UVLO (under voltage
lockout) and a limitation of the max H-level at 11.0 V during normal
operation. In order to turn on the MOSFET softly (with a reduced di_DRAIN/dt),
the gate voltage rises typically within 245 ns from L-level to H-level. The fall
time of the gate voltage is less than 50 ns in order to turn off quickly. This
measure produces different switching speeds during turn-on and turn-off as it
is usually achieved with a diode parallel to a resistor in the gate drive loop. It
is recommended to use a resistor of typically 10 Ω between the drive pin and
gate in order to avoid oscillations and in order to shift the power dissipation
when discharging the gate capacitance into this resistor. The typical dead
time between the LSGD signal and HSGD signal is self-adapting between
500 ns and 1.0 µs.
Low-side current sense signal
This pin is directly connected to the shunt resistor, which is located between
the source terminal of the low-side MOSFET of the inverter and ground.
Internal clamping structures and filtering measures allow sensing of the
source current for the low side inverter MOSFET without additional filter
components.
There is a first threshold of 0.8 V. If this threshold is exceeded for longer
than 500 ns during run mode, an inverter overcurrent is detected, which
causes a latched shutdown of the IC. The saturation control is activated if the
sensed slope at the LSCS pin reaches typical values of 205 mV/µs ±
25 mV/µs and exceeds the 0.8 V threshold. The saturation regulator is now
continuously monitored by the LSCS pin during saturation control mode. In
saturation control mode, the regulator is designed to handle a choke
operation in saturation. If the sensed current signal exceeds a second
threshold of 1.6 V for longer than 500 ns before entering the run mode, the
IC changes over into a latched shutdown.
There are further thresholds active at this pin during run mode that detects
capacitive mode operation. A voltage level below -50 mV before the high-
side gate is on indicates faulty operation (operation below resonance).
A second threshold at 2.0 V senses even short over currents during turn-on
of the high-side MOSFET such as is typical for reverse recovery currents of
a diode. If one of these comparator thresholds indicates incorrect operating
conditions for longer than 620 µs in run mode, the IC turns off the gates and
changes to fault mode due to detected capacitive mode operation (non-zero
voltage switching).
The threshold of -50 mV is also used to adjust the dead time between turn-
off and turn-on of the RESONANT drivers in a range of 500 ns to 1.0 µs
during all operating modes.
Chip supply voltage
This pin provides the power supply of the ground-related section of the IC.
There is a turn-on threshold at 14.0 V and a UVLO threshold at 10.6 V. The
upper supply voltage level is 17.5 V. There is an internal Zener diode
clamping V_CC at 16.3 V (at I_VCC = 2 mA typically). The maximum Zener
current is internally limited to 5 mA. An external Zener diode is required for
higher current levels. Current consumption during UVLO and during fault
mode is less than 170 µA. A ceramic capacitor close to the supply and GND
pin is required in order to act as a low-impedance power source for gate
drive and logic signal currents. In the event of a short interruption to the
mains supply, feed the start-up current (160 µA) from the bus voltage.
Datasheet
6
Rev. 1.3, 2016-01-15