HYS64V64220GU Datasheet, PDF (6/15 Pages) Infineon Technologies AG – 3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules

HYS 64/72V64220GU
SDRAM-Modules
Operating Currents per SDRAM Component
T_A = 0 to 70 ^oC, V_DD = 3.3 V ± 0.3 V
Parameter
Operating current
Test
Condition
–
t_RC = t_RC(MIN.), t_CK = t_CK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
Precharge stand-by current
in Power Down Mode
t_CK = min.
Symbol -7/ -7.5 -8
max.
I_CC1
230
170
I_CC2P
2
2
Unit Note
mA ^{1, 2}
mA ^{1, 2}
CS = V_IH(MIN.), CKE ≤ V_IL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
t_CK = min.
I_CC2N
40
30
mA ^{1, 2}
CS = V_{IH (MIN.)}, CKE ≥ V_IH(MIN.)
No operating current
t_CK = min., CS = V_IH(MIN.),
active state (max. 4 banks)
Burst operating current
t_CK = min.,
Read command cycling
Auto refresh current
t_CK = min.,
Auto Refresh command cycling
Self refresh current
Self Refresh Mode, CKE = 0.2 V
CKE ≥ V_IH(MIN.) I_CC3N
50
CKE ≤ V_IL(MAX.) I_CC3P
10
–
I_CC4
150
45
10
100
mA ^{1, 2}
mA ^{1, 2}
mA ^1,2,3
–
I_CC5
240
220
mA ^{1, 2}
I_CC6
3
3
mA ¹
Notes
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation
frequency for -7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during t_CK, excepts for I_CC6 and for stand-by currents when
t_CK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the data out current is excluded.
INFINEON Technologies
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