HYS64V64220GU Datasheet, PDF (12/15 Pages) Infineon Technologies AG – 3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules

HYS 64/72V64220GU
SDRAM-Modules
SPD-Table for 64M x 72 (512 MByte ECC) Modules HYS72V64220GU
Byte# Description
SPD Entry Value
0
Number of SPD Bytes
128
1
Total Bytes in Serial PD
256
2
Memory Type
SDRAM
3
Number of Row Addresses
13
4
Number of Column Addresses
10
5
Number of DIMM Banks
2
6
Module Data Width
72
7
Module Data Width (cont’d)
0
8
Module Interface Levels
LVTTL
9
SDRAM Cycle Time at CL = 3
7.5 / 10 ns
10
Access Time from Clock at CL = 3
5.4 / 6 ns
11
DIMM Config
ECC
12
Refresh Rate/Type
Self-Refresh,
7.8 µs
13
SDRAM Width, Primary
x8
14
Error Checking SDRAM Data Width
x8
15
Minimum Clock Delay for Back-to-
Back Random Column Address
t_CCD = 1 CLK
16
Burst Length Supported
1, 2, 4 & 8
17
Number of SDRAM Banks
4
18
Supported CAS Latencies
CL = 2 & 3
19
CS Latencies
CS latency = 0
20
WE Latencies
Write latency = 0
21
SDRAM DIMM Module Attributes
unbuffered
22
SDRAM Device Attributes: General
V_DD tol +/– 10%
23
SDRAM Cycle Time at CL = 2
7.5 / 10.0 ns
24
Access Time from Clock for CL = 2
5.4 / 6.0 ns
25
Minimum Clock Cycle Time at CL = 1 not supported
26
Maximum Data Access Time from
not supported
Clock at CL = 1
27
Minimum Row Precharge Time
15 / 20 ns
28
Minimum Row Active to Row Active
14 / 15 / 16 ns
Delay t_RRD
29
Minimum RAS to CAS Delay t_RCD
30
Minimum RAS Pulse Width t_RAS
31
Module Bank Density (per bank)
15 / 20 ns
42 / 45 / 50 ns
256 MByte
32
SDRAM Input Setup Time
1.5 / 2.0 ns
33
SDRAM Input Hold Time
0.8 / 1.0 ns
Hex
64M x 72
-7
-7.5
-8
80
08
04
0D
0A
02
48
00
01
75
75
A0
54
54
60
02
82
08
08
01
0F
04
06
01
01
00
0E
75
A0
A0
54
60
60
00
FF
FF
00
FF
FF
0F
14
14
0E
0F
10
0F
14
14
2A
2D
32
40
15
15
20
08
08
10
INFINEON Technologies
12
9.01