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C161K Datasheet, PDF (58/66 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller
◁
C161K
C161O
AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min. max.
min.
max.
ALE high time
t5 CC 11 + tA –
Address setup to ALE t6 CC 5 + tA –
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
t8 CC 15 + tA –
t9 CC -10 + tA –
t12 CC 34 + tC –
t13 CC 59 + tC –
t14 SR –
22 + tC
t15 SR –
47 + tC
t16 SR –
t17 SR –
t18 SR 0
45 +
tA + tC
57 +
2tA + tC
–
TCL - 14 –
ns
+ tA
TCL - 20 –
ns
+ tA
TCL - 10 –
ns
+ tA
-10
–
ns
+ tA
2TCL - 16 –
ns
+ tC
3TCL - 16 –
ns
+ tC
–
2TCL - 28 ns
+ tC
–
3TCL - 28 ns
+ tC
–
3TCL - 30 ns
+ tA + tC
–
4TCL - 43 ns
+ 2tA + tC
0
–
ns
Data float after RD rising t20 SR –
edge (with RW-delay1))
Data float after RD rising t21 SR –
edge (no RW-delay1))
36 +
–
2tA + tF1)
15 +
–
2tA + tF1)
2TCL - 14 ns
+ 22tA
+ tF1)
TCL - 10 ns
+ 22tA
+ tF1)
Data Sheet
54
V2.0, 2001-01
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