C161K Datasheet, PDF (50/66 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C161K
C161O
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2t_A + t_C + t_F (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min. max. min.
max.
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
t₅₀ CC 28 + t_C
t₅₁ SR 0
t₅₂ SR –
t₅₄ CC 30 + t_F
t₅₆ CC 30 + t_F
–
–
30 + t_F
–
–
2TCL - 22 –
ns
+ t_C
0
–
ns
–
2TCL - 20 ns
+ t_F
2TCL - 20 –
ns
+ t_F
2TCL - 20 –
ns
+ t_F
1) _{These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are}
specified together with the address and signal BHE (see figures below).
Data Sheet
46
V2.0, 2001-01