C161K Datasheet, PDF (40/66 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C161K
C161O
AC Characteristics
Definition of Internal Timing
The internal operation of the C161K/O is controlled by the internal CPU clock f_CPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).
Direct Clock Drive
f_OSC
f_CPU
Prescaler Operation
f_OSC
f_CPU
TCL
TCL
TCL
TCL
MCT04826
Figure 8 Generation Mechanisms for the CPU Clock
The CPU clock signal f_CPU can be generated from the oscillator clock signal f_OSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate f_CPU. This influence must
be regarded when calculating the timings for the C161K/O.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9 associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet
36
V2.0, 2001-01