SAB80C166W Datasheet, PDF (57/67 Pages) Siemens Semiconductor Group – C16x-Family of High-Performance CMOS 16-Bit Microcontrollers

SAB 80C166W/83C166W
AC Characteristics (cont’d)
Demultiplexed Bus
V_CC = 5 V ± 10 %; V_SS = 0 V
T_A = 0 to + 70 ˚C for SAB 83C166W-5M, SAB 80C166W/83C166W-M
T_A = – 40 to + 85 ˚C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3
T_A = – 40 to + 110 ˚C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4
C_L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
ALE cycle time = 4 TCL (100 ns at 20-MHz CPU clock)
Parameter
ALE high time
Address setup to ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay)
Data float after RD rising
edge (no RW-delay)
Data valid to WR
Symbol CPU Clock = 16 MHz Variable CPU Clock Unit
Duty cycle 0.4 to 0.6
1/T_CLP = 1 to 20 MHz
min.
max.
min.
max.
t₅ CC 15 + t_A
t₆ CC 10 + t_A
t₈ CC 15 + t_A
t₉ CC -10 + t_A
t₁₂ CC 52.5 + t_C
t₁₃ CC 77.5 + t_C
t₁₄ SR –
t₁₅ SR –
t₁₆ SR –
t₁₇ SR –
t₁₈ SR 0
–
T_CLmin - 10 –
ns
+ t_A
–
T_CLmin - 15 –
ns
+ t_A
–
T_CLmin - 10 –
ns
+ t_A
–
-10
–
ns
+ t_A
–
T_CLP - 10
–
ns
+ t_C
–
T_CLP+T_CLmin –
ns
- 10 + t_C
47.5 + t_C –
T_CLP - 20
ns
+ t_C
72.5 + t_C –
T_CLP+T_CLmin ns
- 20 + t_C
72.5
–
+ t_A + t_C
T_CLP+T_CLmin ns
- 20 + t_A + t_C
100
–
+ 2 t_A + t_C
2T_CLP - 25 ns
+ 2t_A + t_C
–
0
–
ns
t₂₀ SR –
47.5 + t_F –
t₂₁ SR –
15 + t_F
–
t₂₂ CC 47.5 + t_C –
T_CLP - 15
+ t_C
T_CLP - 15
ns
+ t_F
T_CLmin - 10 ns
+ t_F
–
ns
Semiconductor Group
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