SAB80C166W Datasheet, PDF (10/67 Pages) Siemens Semiconductor Group – C16x-Family of High-Performance CMOS 16-Bit Microcontrollers

SAB 80C166W/83C166W
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the SAB 80C166W/83C166W’s instructions can be
executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of the number
of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed
very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division
in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the
execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register banks may overlap others.
32 KByte in the
SAB 83C166W
Figure 4
CPU Block Diagram
Semiconductor Group
10
1 KByte