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C517A Datasheet, PDF (56/72 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller
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C517A
Power Supply Current
Parameter
Active mode
Idle mode
Active mode with
slow-down enabled
Power-down mode
18 MHz
24 MHz
18 MHz
24 MHz
18 MHz
24 MHz
Symbol
Limit Values
typ. 9)
max. 10)
IDD
21.3
29.2
IDD
27.3
37.6
IDD
11.6
16.2
IDD
14.6
20.4
IDD
9.5
13.1
IDD
10.7
14.9
IPD
15
50
Unit Test Condition
mA 4)
mA
mA 5)
mA
mA 6)
mA
µA VDD = 2…5.5 V 3)
Notes:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD
specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = RESET = Port 0 = Port 7 = Port 8 = VDD ; XTAL1 = N.C.; XTAL2 = VSS ; PE/SWD = OWE = VSS ;
HWPD = VDD for software power-down mode; VAGND = VSS ; VAREF = VDD ; all other pins are disconnected.
IPD (hardware power-down mode) is independent of any particular pin connection.
4) IDD (active mode) is measured with:
XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
EA = PE/SWD == VSS ; Port 0 = Port 7 = Port 8 = VDD ; HWPD = VDD ; RESET = VDD ; all other pins are
disconnected.
5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
RESET = VDD ; HWPD = Port 0 = Port 7 = Port 8 = VDD ; EA = PE/SWD = VSS ;
all other pins are disconnected;
6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
HWPD = VDD ; RESET = VDD ; Port 7 = Port 8 = VDD ;; EA = PE/SWD == VSS ; all other pins are disconnected.
7) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port
pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits.
8) Not 100% tested, guaranteed by design characterization
9) The typical IDD values are periodically measured at TA = +25 °C and VDD = 5 V but not 100% tested.
10)The maximum IDD values are measured under worst case conditions (TA = 0 °C or -40 °C and VDD = 5.5 V)
Semiconductor Group
54
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