TLE82452-3SA_15 Datasheet, PDF (51/71 Pages) Infineon Technologies AG – 2 Channel High-Side and Low-Side Linear Solenoid Driver IC

11.3
Electrical Characteristics SPI Interface
TLE82452-3SA
Serial Peripheral Interface (SPI)
Table 11 Electrical Characteristics: SPI
V_BAT = 8 V to 17 V, V_DDx = 4.75 V to 5.25 V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Number
Min. Typ. Max.
Test Condition
Serial clock frequency
f_SCLK
–
–
8
MHz ^{1) 2)}
Serial clock high time
t_SCLKH
50
–
–
ns
1)
Serial clock low time
t_SCLKL
50
–
–
ns
1)
Enable lead time (falling CSN t_{CSN_LEAD} 250
–
–
ns
1)
to rising SCLK)
P_11.3.1
P_11.3.2
P_11.3.3
P_11.3.4
Enable lag time (falling SCLK t_{CSN_LAG}
250
–
–
ns
1)
to rising CSN)
P_11.3.5
Transfer delay time (rising t_{CSN_TD}
5
–
–
cycles F_sys cycles ¹⁾
P_11.3.6
CSN to falling CSN)
Data setup time (required
time SI to falling SCLK)
t_{SI_SU}
20
–
–
ns
1)
P_11.3.7
Data hold time (required time t_{SI_H}
falling SCLK to SI)
20
–
–
ns
1)
P_11.3.8
Output enable time (falling t_{SO_EN}
–
–
200
ns
C_L = 200 pF ¹⁾
P_11.3.9
CSN to SO valid)
Output disable time (rising t_{SO_DIS}
–
–
200
ns
C_L = 200 pF ¹⁾
P_11.3.10
CSN to SO tri-state)
Output data valid time with
capacitive load
t_{SO_V}
–
–
100
ns
C_L = 200 pF ¹⁾
P_11.3.11
SO rise time
SO fall time
Input pin capacitance: CSN,
SCLK, SI, CLK
t_{SO_R}
t_{SO_F}
C_IN
–
–
50
ns
C_L = 200 pF ¹⁾
P_11.3.12
–
–
50
ns
C_L = 200 pF ¹⁾
P_11.3.13
–
–
20
pF
1)
P_11.3.14
SO pin capacitance
C_{SO_HIZ}
–
–
25
pF Tri-state ¹⁾
P_11.3.15
1) Not subject to production test, specified by design.
2) Maximum SPI clock frequency in the application may be less depending on the load at the SO pin and the microcontroller
SPI peripheral timing requirements.
Data Sheet
-
51
Rev 1.0, 2015-03-27