TLE82452-3SA_15 Datasheet, PDF (13/71 Pages) Infineon Technologies AG – 2 Channel High-Side and Low-Side Linear Solenoid Driver IC

5
Input / Output
TLE82452-3SA
Input / Output
5.1
I/O Description
The CLK pin must be connected to a precise clock signal. This clock is used by the internal analog to digital
converters and by the internal logic. A small internal pull down current will keep the voltage on this pin near ground
when the pin is open. The device includes a programmable divider to generate the internal system clock from the
CLK pin signal. This divider ratio is programmed in the CLK-DIVIDER register by the SPI interface. The output
stages cannot be enabled until this field has been written.
An internal watchdog circuit will hold the device in an internal reset state if the delay between rising edges on the
CLK pin is greater than the threshold time, T_{CLK_MSS}. The watchdog is initially disabled when the device exits the
reset state. The watchdog is enabled by setting the WDEN bit in the CLK-DIVIDER register. If the watchdog is
enabled, there are no settings which can prevent the fault pin being pulled low during a WD event.
Until the watchdog is enabled, the output stages are disabled. Once the watchdog function is enabled, a missing
CLK signal will set the Watchdog Status Bit in the IC VERSION register, set the FAULTN pin to a logic low state,
disable the output stages, and cause the device to enter an internal reset state. If the CLK signal is missing, the
SPI response from the device will always be the response to an IC VERSION register read command. If the CLK
signal returns after the watchdog function has triggered, the SPI response to a specific register read command will
be the reset value of the specific register, except of the ICVID Register that is indicating the Watchdog timeout
fault. Be aware that the CLK-DIVIDER is reset to 8 when the CLK is lost and than returns, which affects the system
clock frequency (F_SYS = F_CLK/8) and thus the transfer delay time (see P_11.3.6).
In both cases it is not possible to write to any SPI register. To return to normal operation and exit this internal reset
state the device must be reset externally by the RESN pin or an power on reset must be performed.
The EN pin is used to enable / disable the output stages. If the EN pin is low, all of the channels are disabled and
(when the fault mask bit FME = 1) the FAULTN pin is pulled low. The SPI interface remains functional. However,
when the EN pin is low, the EN bits in the SET-POINT registers are cleared. The EN pin can be connected to a
general purpose output pin of the microcontroller or to an output of a safing circuit. However, all other SPI register
settings remain unchanged. After the EN pin goes high the EN bits in the set point registers remain 0 until they are
changed to 1. The EN bits will immediately return to 0 if the EN pin is low.
The RESN pin is the reset input for the device. If the RESN pin is low, the device is held in an internal reset state,
the FAULTN pin is held low, and the SPI interface is disabled. An internal pull down current source will hold the
RESN pin low in case the pin is open.
The FAULTN pin is an open drain output. This pin is pulled low when a fault is detected by the diagnosis circuit or
when the device is in an internal reset state. An external resistor should be connected between this pin and the
VIO supply.
The SI, SO, CSN, and SCLK pins comprise the SPI interface. See Chapter 11and Chapter 12 for details.
Data Sheet
-
13
Rev 1.0, 2015-03-27