HYB39S64400CT-7.5 Datasheet, PDF (50/52 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

21. Full Page Write Cycle
21.1 CAS Latency = 2
HYB39S64400/800/160CT(L)
64MBit Synchronous DRAM
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t _CK2
CKE High
CS
RAS
CAS
WE
BS
AP
RAx
RBx
RBy
Addr. RAx
CAx
RBx
CBx
RBy
DQM
Hi-Z
DQ
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Activate Write Activate
Command Command Command
Bank A Bank A Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Write
Command
Bank B
Data is Burst Stop
ignored. Command
Activate
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Precharge
Command
Bank B
SPT03931
Semiconductor Group
50