HYB39S64400CT-7.5 Datasheet, PDF (33/52 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

HYB39S64400/800/160CT(L)
64MBit Synchronous DRAM
12. Clock Suspension ( Using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t _CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
DQM
Hi-Z
DQ
t _CSL
t _CSL
t _CSL
t _HZ
Ax0 Ax1
Ax2
Ax3
Activate Read
Command Command
Bank A Bank A
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03914
Semiconductor Group
33