HYB39S64400CT-7.5 Datasheet, PDF (28/52 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

HYB39S64400/800/160CT(L)
64MBit Synchronous DRAM
8. Burst Termination
8.1 Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command Read A NOP
NOP
NOP
Burst
Terminate
NOP
NOP
NOP
NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
The burst ends after a delay equal to the CAS latency.
SPT03722
8.2 Termination of a Full Page Burst Write Operation
(
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
NOP Write A NOP
NOP
Burst
Terminate
NOP
NOP
NOP
NOP
CAS
latency = 2, 3
DQ’s
DIN A0 DIN A1 DIN A2 don’t care
Input data for the Write is masked.
SPT03419
Semiconductor Group
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