XC2220U Datasheet, PDF (48/105 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2220U
XC2000 Family / Compact Line
Functional Description
it overflows. If this is not the case because of a hardware or software failure, the Window
Watchdog Timer overflows, generating a reset request.
The Window Watchdog Timer has a ‘programmable window boundary’, it disallows
refresh during the Window Watchdog Timer’s count-up. A refresh during this window-
boundary will cause the Window Watchdog Timer to also generate a reset request.
The Window Watchdog Timer is a 16-bit timer clocked with either the system clock or the
independent wake-up oscillator clock, divided by 16,384 or 256. The Window Watchdog
Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow
further variation of the monitored time interval. Each time it is serviced by the application
software, the Window Watchdog Timer is reloaded.
When clocked by f_SYS = 66 MHz, time intervals between 15.2 ns and 16.3 s can be
monitored.
When clocked by f_WU = 500 kHz, time intervals between 2.0 µs and 2147.5 s can be
monitored.
The default Watchdog Timer interval after power-up is 0.13 s (@ f_WU = 500 kHz).
3.15
Clock Generation
The Clock Generation Unit can generate the system clock signal f_SYS for the XC2220U
from a number of external or internal clock sources:
• External clock signals with pad voltage or core voltage levels
• External crystal or resonator using the on-chip oscillator
• On-chip clock source for operation without crystal/resonator
• Wake-up clock (ultra-low-power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.7.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on the EXTCLK pin.
Data Sheet
44
V1.2, 2012-07