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XC2220U Datasheet, PDF (26/105 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance | |||
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XC2220U
XC2000 Family / Compact Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC2220U is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC2220U Memory Map 1)
Address Area
Start Loc. End Loc. Area Size2) Notes
IMB register space
Reserved
FFâFF00H FFâFFFFH 256 bytes
F0â0000H FFâFEFFH < 1 Mbyte
Minus IMB
registers.
Reserved for EPSRAM
Emulated PSRAM
Reserved for PSRAM
PSRAM
Reserved for Flash
Flash 0
External memory area
External IO area4)
Reserved
USIC0 alternate regs.
E8â1000H
E8â0000H
E0â1000H
E0â0000H
C1â1000H
C0â0000H
40â0000H
21â0000H
20âB400H
20âB000H
EFâFFFFH
E8â0FFFH
E7âFFFFH
E0â0FFFH
DFâFFFFH
C1â0FFFH
BFâFFFFH
3FâFFFFH
20âFFFFH
20âB3FFH
508 Kbytes Mirrors EPSRAM
up to 4 Kbytes With Flash timing.
508 Kbytes Mirrors PSRAM
up to 4 Kbytes Program SRAM.
1980 Kbytes
68 Kbytes3)
8 Mbytes
1984 Kbytes
19 Kbytes
1 Kbytes
Accessed via
LXBus controller
Reserved
USIC0 registers
20â4800H 20âAFFFH 26 Kbytes
20â4000H 20â47FFH 2 Kbytes
Accessed via
LXBus controller
Reserved
External memory area
SFR area
Dual-port RAM
(DPRAM)
20â0000H
01â0000H
00âFE00H
00âF600H
20â3FFFH
1FâFFFFH
00âFFFFH
00âFDFFH
16 Kbytes
1984 Kbytes
0.5 Kbytes
2 Kbytes
Reserved for DPRAM
ESFR area
XSFR area
Data SRAM (DSRAM)
00âF200H
00âF000H
00âE000H
00âD800H
00âF5FFH
00âF1FFH
00âEFFFH
00âDFFFH
1 Kbytes
0.5 Kbytes
4 Kbytes
2 Kbytes
Data Sheet
22
V1.2, 2012-07
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