XC2220U Datasheet, PDF (25/105 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2220U
XC2000 Family / Compact Line
Functional Description
3
Functional Description
The architecture of the XC2220U combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC2220U.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC2220U.
PSRAM
Flash Memory
System Functions
Clock, Reset, Power
Control
DPRAM
DSRAM
CPU
MAC Unit
MPU
Interrupt & PEC
Interrupt Bus
OCDS
Debug Support
LXBUS
Controller
MCHK
WWD
RTC
ADC0
Module
GPT
CC2 CCU6 0
Module Module
USIC0
Module
8-/10- /
12 -Bit
5
Timers
16
Chan.
3+1
Chan.
2
Chan.
Analog and Digital General Purpose IO (GPIO) Ports
Figure 3 Block Diagram
Data Sheet
21
MC_U- SERIES_BLOCKDIAGRAM
V1.2, 2012-07