TC1910 Datasheet, PDF (48/66 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

PRELIMINARY
TC1910
±5.0
ns
D_N
±4.0
TC191x_pll_jitter
±3.0
±2.0
±1.0
f_SYS = 66 MHz (K = 4)
f_SYS = 60 MHz (K = 5)
f_SYS = 50 MHz (K = 6)
f_SYS = 40 MHz (K = 7)
f_SYS = 33 MHz (K = 8)
±0.0
0
5
10
15
20
25
D_N = Max. jitter
P = Number of consecutive f_SYS periods
K _{= K-divider of PLL}
30
35
P
Figure 14 Approximated Maximum Accumulated PLL Jitter
The following two formulas define the (absolute) approximate maximum value of jitter D_N
in [ns] dependent on the K-factor, the system clock frequency f_SYS in [MHz], and the
number P of consecutive f_SYS periods.
for P < 0.25× f_SYS
D_N [ns] =
± [( ⁷³⁵
f_SYS × K
+ 0.9) ×
P
+ 0.5 ] [1]
f_SYS × 0.25
for P > _{0.25× fSYS}
D_N [ns] =
± [ ⁷³⁵
f_SYS ×
K
+ 1.4 ]
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a specific
value of P. Beyond this value of P the maximum accumulated jitter remains at a constant
value.
Data Sheet
44
V 1.0, 2003-10