TC1910 Datasheet, PDF (20/66 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

PRELIMINARY
TC1910
LMB Bus 64-bit
FPI Bus 32-bit
EBU_LMB
XBC
DME
XMI
External Bus Unit
SDRAM
Buffer
S lo w e r
D e v ic e s
50 MHz
External
M aster
EBUL3045_L
Figure 4 EBU_LMB block diagram
Features supported in EBU_LMB:
• Local Memory Bus (LMB 64-bit) support.
• External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.
• Highly programmable access parameters.
• Intel-style and Motorola-style peripheral/device support.
• SDRAM support (burst access, multibanking, precharge, refresh).
• 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.
• Burst flash support.
• Multiplexed access (address & data on the same bus) when DRAM is not present on
the External Bus.
• Data Buffering: Code Prefetch Buffer, Read/Write Buffer.
• External master arbitration (compatible to C166 and other TriCore devices).
• 8 programmable address regions (1 dedicated for emulator).
• Little-Endian and Big-Endian support.
• CSglb signal, dedicated pin, bit programmable to combine one or more CS lines, for
buffer control.
• RMW signal reflecting a read-modify-write action.
• Signal for controlling data flow of slow-memory buffer.
• Slave unit for external (off-chip) master to access devices on the FPI bus.
• Master unit for FPI master to access external (off-chip) devices.
• Data Mover Engine.
Data Sheet
16
V 1.0, 2003-10