C501 Datasheet, PDF (38/48 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C501
AC Characteristics for C501-L40 / C501-1R40 (cont’d)
External Data Memory Characteristics
Parameter
RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
Symbol
Limit Values
Unit
40 MHz
Clock
min. max.
Variable Clock
1/t_CLCL = 3.5 MHz to 40 MHz
min.
max.
t_RLRH
120 –
6 t_CLCL– 30
–
ns
t_WLWH
120 –
6 t_CLCL– 30
–
ns
t_LLAX2
10
–
t_CLCL– 15
–
ns
t_RLDV
–
75 –
5 t_CLCL– 50
ns
t_RHDX
0
–
0
–
ns
t_RHDZ
–
38 –
2 t_CLCL– 12
ns
t_LLDV
–
150 –
8 t_CLCL– 50
ns
t_AVDV
–
150 –
9 t_CLCL– 75
ns
t_LLWL
60
90
3 t_CLCL– 15
3 t_CLCL+ 15
ns
t_AVWL
70
–
4 t_CLCL– 30
–
ns
t_WHLH
10
40
t_CLCL– 15
t_CLCL+ 15
ns
t_QVWX
5
–
t_CLCL– 20
–
ns
t_QVWH
125 –
7 t_CLCL– 50
–
ns
t_WHQX
5
–
t_CLCL– 20
–
ns
t_RLAZ
–
0
–
0
ns
External Clock Drive Characteristics
Parameter
Symbol
Oscillator period
High time
Low time
Rise time
Fall time
t_CLCL
t_CHCX
t_CLCX
t_CLCH
t_CHCL
min.
25
10
10
–
–
Limit Values
Variable Clock
Freq. = 3.5 MHz to 40 MHz
max.
285.7
t t – _{CLCL CLCX}
t t – _{CLCL CHCX}
10
10
Unit
ns
ns
ns
ns
ns
Semiconductor Group
38
1997-04-01