XC164N Datasheet, PDF (36/68 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164N
Derivatives
Functional Description
f_SYS
T2IN
T2EUD
f_SYS
T3IN
T3EUD
f_SYS
T4IN
T4EUD
2ⁿ : 1
2ⁿ : 1
GPT1 Timer T2
T2
Mode
Control
U /D
Reload
Capture
T3
Mode
Control
GPT1 Timer T3
U /D
Toggle FF
T3OTL
Interrupt
Request
(T2IR)
Interrupt
Request
(T3IR)
T6OUT
2ⁿ : 1
Capture
Reload
T4
Mode
Control
GPT1 Timer T4
U /D
Interrupt
Request
(T4IR)
n = 2 … 12
M ct04825_xc.vsd
Figure 7 Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
Data Sheet
31
V1.0, 2005-01