|
XC164N Datasheet, PDF (29/68 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core | |||
|
◁ |
XC164N
Derivatives
Functional Description
The XC164N also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called âHardware Trapsâ.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location1) Number Priority
Reset Functions:
â
â Hardware Reset
â Software Reset
â W-dog Timer Overflow
RESET
xxâ0000H 00H
III
RESET
xxâ0000H 00H
III
RESET
xxâ0000H 00H
III
Class A Hardware Traps:
â Non-Maskable Interrupt NMI
NMITRAP xxâ0008H 02H
II
â Stack Overflow
STKOF STOTRAP xxâ0010H 04H
II
â Stack Underflow
STKUF STUTRAP xxâ0018H 06H
II
â Software Break
SOFTBRK SBRKTRAP xxâ0020H 08H
II
Class B Hardware Traps:
â Undefined Opcode
UNDOPC BTRAP
xxâ0028H 0AH
I
â PMI Access Error
PACER BTRAP
xxâ0028H 0AH
I
â Protected Instruction PRTFLT BTRAP
xxâ0028H 0AH
I
Fault
â Illegal Word Operand ILLOPA BTRAP
xxâ0028H 0AH
I
Access
Reserved
â
â
[2CH â
3CH]
Software Traps
â
â
Any
â TRAP Instruction
[xxâ0000H â
xxâ01FCH]
in steps
of 4H
1) Register VECSEG defines the segment where the vector table is located to.
[0BH â
0FH]
Any
[00H â
7FH]
â
Current
CPU
Priority
Data Sheet
24
V1.0, 2005-01
|
▷ |