XC164N Datasheet, PDF (21/68 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164N
Derivatives
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC164N Memory Map¹⁾
Address Area
Start Loc. End Loc. Area Size²⁾ Notes
Flash register space
Reserved (Acc. trap)
Reserved for PSRAM
FF’F000_H
F8’0000_H
E0’0800_H
FF’FFFF_H
FF’EFFF_H
F7’FFFF_H
4 Kbytes
<0.5 Mbytes
<1.5 Mbytes
Flash only³⁾
Minus Flash regs
Minus PSRAM
Program SRAM
E0’0000_H E0’07FF_H
2 Kbytes Maximum
Reserved for pr. mem. C2’0000_H DF’FFFF_H < 2 Mbytes Minus Flash
Program Flash
Reserved
External memory area
External IO area⁴⁾
Reserved
External memory area
C0’0000_H
BF’0000_H
40’0000_H
20’0800_H
20’0000_H
01’0000_H
C1’FFFF_H
BF’FFFF_H
BE’FFFF_H
3F’FFFF_H
20’07FF_H
1F’FFFF_H
128 Kbytes
64 Kbytes
< 8 Mbytes
< 2 Mbytes
2 Kbytes
< 2 Mbytes
up to 128 Kbytes
Minus res. seg.
Minus segment 0
Data RAMs and SFRs 00’8000_H 00’FFFF_H 32 Kbytes
External memory area 00’0000_H 00’7FFF_H 32 Kbytes
1) Accesses to the shaded areas generate external bus accesses.
Partly used
2) The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
16
V1.0, 2005-01