TLE4997 Datasheet, PDF (30/36 Pages) Infineon Technologies AG – Programmable Linear Hall Sensor for Industrial Use

TLE4997I
Calibration
9.1
Calibration Data Memory
When the MEMLOCK bits are programmed (two redundant bits), the memory contents
are frozen and may no longer be changed. Furthermore, the programming interface is
locked out and the chip remains in Application Mode only. This prevents accidental
programming due to environmental influences.
Column Parity Bits
User-Calibration Bits
Pre-Calibration Bits
Figure 9 EEPROM Map
A matrix parity architecture allows the automatic correction of any single bit error. Each
row is protected by a row parity bit. The sum of bits set including this bit must be an odd
number (ODD PARITY). Each column is additionally protected by a column parity bit.
The sum of all the bits in the even positions (0, 2, etc.) of all lines must be an even
number (EVEN PARITY); the sum of all the bits in the odd positions (1,3, etc.) must be
an odd number (ODD PARITY). This mechanism of different parity calculations protects
against many block errors (such as erasing a full line or even the entire EEPROM).
When modifying the application bits (such as Gain, Offset, TC, etc.) the parity bits must
be updated. For the column bits, the pre-calibration area must be also read out and
considered for correct parity generation.
Note: A specific programming algorithm must be followed to ensure the data retention.
A separate detailed programming specification is available on request.
Data Sheet
30
V 1.0, 2007-06